TESCA Digital I.C. Trainer

SPECIFICATIONS

1. + 5V DC at 1Amp, IC Regulated Power Supply.
2. 0Fourteen , two position toggle switches pre-wired     to give binary logic input states.
3. Fourteen , LED logic indicators with transistor     drivers.
4. 3 digit Seven Segment Displays with decoder driver an provision to take-out output for monitoring.
5. Clock Generators Fixed : (1) 1Hz ( 2) 1KHz. (3) 1MHz (Simultaneous independent outputs ).
6. Single pulse from mono pulser.
7. IC BASE 8, 14, 16 Pin 3 No. and 24, 28Pin 1No. gold/silver plated Zero Insertion Force (ZIF) dual in line Package (DIP) on Front Panel.
8. Components Provided : ICs-555/1, 4001/1,4008/1, 4011/1, 4013/1, 4018/1, 4027/1, 4045/1, 4098/1, 7400/1, 7402/1, 7404/1, 7407/1, 7408/1,7411/1, 7432/1, 7472/1, 7473/2, 7480/1, 7486/1, 7489/1, 7490/3, 7493/1, 7496/1, 74121/1 74181/1, 74194/1 total = 30
9. Accessories : Mains cord, Operating and Experimental manual, Red & Black patch cords 18 each
10. Instruction manual : Strongly supported by detailed operating instructions.
11. Wiring of all types of experiments become simple and less time consuming.
12. Adequate no. of other Electronic Components.
13. The unit is operative on 230V ±10% at 50Hz A.C. Mains.
14. Weight : 4.700 Kg. (Approx.)
15. Dimension : W415 x H165 x D 315.

THE TRAINER COVER THE FOLLOWING EXPERIMENT LOGIC GATES
01     AND GATE (DIODE & TTL LOGIC)
02     OR GATE (DIODE LOGIC)
03     NAND GATE (TTL)
04     NOR GATE (TTL)
05     NOT GATE (TTL)
06     EXCLUSIVE – OR GATE (TTL)
BOOLEAN ALGEBRA
07     TO PROVE BOOLEAN THEOREMS A + = 1
08     TO PROVE BOOLEAN THEOREM A + A . B = A
TO PROVE DEMORGAN’S THEOREMS
09    A + B = A . B
10    A . B = A +B
MONOSTABLE (TTL)
11     NEGATIVE EDGE TRIGGERED MONOSTABLE
12     SCHMITT TRIGGER
FLIP FLOP (TTL)
13     RS FLIP FLOP
14     CLOCKED RS FLIP FLOP
15     J. K. FLIP-FLOP
BINARY COUNTERS (TTL)
16     BINARY RIPPLE COUNTER
17     SYNCHRONOUS COUNTER
DIVIDE BY N COUNTER
18     DIVIDE BY 6 COUNTER USING 7493 IC
19     DIVIDE BY 60 COUNTER USING 7493 AND 7490 IC’S
20     RING COUNTER
FULL & HALF ADDERS (TTL)
21     HALF ADDER
22     FULL ADDER
SUBTRACTORS & ARITHMETIC LOGIC UNIT (TTL)
23     HALF & FULL SUBTRACTOR
24     ARITHMATIC LOGIC UNIT
REGISTERS (TTL)
25     SHIFT REGISTER CONSTRUCTED FROM MASTER SLAVE JK FF
26     5 BIT REGISTER (USING 7496)
27     UNIVERSAL SHIFT REGISTER
MEMORIES (TTL)
28     ORGANISATION OF RAM / IC 7489 – RAM
29     ROM (READ ONLY MEMORY)
EXPERIMENT OF CMOS DEVICES
30     NAND CMOS
31     NOR CMOS
32     BOOLEAN ALGEBRA (CMOS)
33     ASTABLE MULTIVIBRATOR & SCHMITT TRIGGER WITH ADJUSTABLE TRIGGERING (CMOS)
34     MONOSTABLE MULTIVIBRATOR (CMOS)
35     FLIP FLOPS (CMOS)
36     HALF & FULL ADDER (CMOS)
37     PRESETTABLE DEVIDE-BY-N COUNTER (CMOS)
38     BINARY TO DECIMAL CONVERSION
39     3 DIGIT STROKE COUNTER USING IC 7490
40     ACCURATE TIMER USING BEL CD 4045 & CD 4013
41     MONOSTABLE OPERATION USING IC 555 TIMER
42     ASTABLE OPERATION USING IC 555 TIMER
43     FREQUENCY MODULATION USING IC 555 TIMER
44     SQUARE WAVE GENERATOR USING IC 555 TIMER