{"id":32353,"date":"2023-05-10T11:26:52","date_gmt":"2023-05-10T11:26:52","guid":{"rendered":"https:\/\/coral-i.co.za\/test-equipment\/?post_type=product&p=32353"},"modified":"2023-05-10T11:26:53","modified_gmt":"2023-05-10T11:26:53","slug":"tesca-digital-i-c-trainer","status":"publish","type":"product","link":"https:\/\/coral-i.co.za\/test-equipment\/product\/tesca-digital-i-c-trainer\/","title":{"rendered":"TESCA Digital I.C. Trainer"},"content":{"rendered":"

SPECIFICATIONS<\/strong><\/p>\n

    \n
  1. + 5V DC at 1Amp, IC Regulated Power Supply.<\/li>\n
  2. 0Fourteen , two position toggle switches pre-wired \u00a0\u00a0 \u00a0to give binary logic input states.<\/li>\n
  3. Fourteen , LED logic indicators with transistor \u00a0\u00a0 \u00a0drivers.<\/li>\n
  4. 3 digit Seven Segment Displays with decoder driver an provision to take-out output for monitoring.<\/li>\n
  5. Clock Generators Fixed : (1) 1Hz ( 2) 1KHz. (3) 1MHz (Simultaneous independent outputs ).<\/li>\n
  6. Single pulse from mono pulser.<\/li>\n
  7. IC BASE 8, 14, 16 Pin 3 No. and 24, 28Pin 1No. gold\/silver plated Zero Insertion Force (ZIF) dual in line Package (DIP) on Front Panel.<\/li>\n
  8. Components Provided :\u00a0ICs-555\/1, 4001\/1,4008\/1, 4011\/1, 4013\/1, 4018\/1, 4027\/1, 4045\/1, 4098\/1, 7400\/1, 7402\/1, 7404\/1, 7407\/1, 7408\/1,7411\/1, 7432\/1, 7472\/1, 7473\/2, 7480\/1, 7486\/1, 7489\/1, 7490\/3, 7493\/1, 7496\/1, 74121\/1 74181\/1, 74194\/1 total = 30<\/li>\n
  9. Accessories : Mains cord, Operating and Experimental manual, Red & Black patch cords 18 each<\/li>\n
  10. Instruction manual : Strongly supported by detailed operating instructions.<\/li>\n
  11. Wiring of all types of experiments become simple and less time consuming.<\/li>\n
  12. Adequate no. of other Electronic Components.<\/li>\n
  13. The unit is operative on 230V \u00b110% at 50Hz A.C. Mains.<\/li>\n
  14. Weight : 4.700 Kg. (Approx.)<\/li>\n
  15. Dimension : W415 x H165 x D 315.<\/li>\n<\/ol>\n

    THE TRAINER COVER THE FOLLOWING EXPERIMENT LOGIC GATES<\/strong>
    \n01 \u00a0\u00a0 \u00a0AND GATE (DIODE & TTL LOGIC)
    \n02 \u00a0\u00a0 \u00a0OR GATE (DIODE LOGIC)
    \n03 \u00a0\u00a0 \u00a0NAND GATE (TTL)
    \n04 \u00a0\u00a0 \u00a0NOR GATE (TTL)
    \n05 \u00a0\u00a0 \u00a0NOT GATE (TTL)
    \n06 \u00a0\u00a0 \u00a0EXCLUSIVE – OR GATE (TTL)
    \nBOOLEAN ALGEBRA<\/strong>
    \n07 \u00a0\u00a0 \u00a0TO PROVE BOOLEAN THEOREMS A + = 1
    \n08 \u00a0\u00a0 \u00a0TO PROVE BOOLEAN THEOREM A + A . B = A
    \nTO PROVE DEMORGAN’S THEOREMS<\/strong>
    \n09\u00a0\u00a0 \u00a0A + B = A . B
    \n10\u00a0\u00a0 \u00a0A . B = A +B
    \nMONOSTABLE (TTL)<\/strong>
    \n11 \u00a0\u00a0 \u00a0NEGATIVE EDGE TRIGGERED MONOSTABLE
    \n12 \u00a0\u00a0 \u00a0SCHMITT TRIGGER
    \nFLIP FLOP (TTL)<\/strong>
    \n13 \u00a0\u00a0 \u00a0RS FLIP FLOP
    \n14 \u00a0\u00a0 \u00a0CLOCKED RS FLIP FLOP
    \n15 \u00a0\u00a0 \u00a0J. K. FLIP-FLOP
    \nBINARY COUNTERS (TTL)<\/strong>
    \n16 \u00a0\u00a0 \u00a0BINARY RIPPLE COUNTER
    \n17 \u00a0\u00a0 \u00a0SYNCHRONOUS COUNTER
    \nDIVIDE BY N COUNTER<\/strong>
    \n18 \u00a0\u00a0 \u00a0DIVIDE BY 6 COUNTER USING 7493 IC
    \n19 \u00a0\u00a0 \u00a0DIVIDE BY 60 COUNTER USING 7493 AND 7490 IC’S
    \n20 \u00a0\u00a0 \u00a0RING COUNTER
    \nFULL & HALF ADDERS (TTL)<\/strong>
    \n21 \u00a0\u00a0 \u00a0HALF ADDER
    \n22 \u00a0\u00a0 \u00a0FULL ADDER
    \nSUBTRACTORS & ARITHMETIC LOGIC UNIT (TTL)<\/strong>
    \n23 \u00a0\u00a0 \u00a0HALF & FULL SUBTRACTOR
    \n24 \u00a0\u00a0 \u00a0ARITHMATIC LOGIC UNIT
    \nREGISTERS (TTL)<\/strong>
    \n25 \u00a0\u00a0 \u00a0SHIFT REGISTER CONSTRUCTED FROM MASTER SLAVE JK FF
    \n26 \u00a0\u00a0 \u00a05 BIT REGISTER (USING 7496)
    \n27 \u00a0\u00a0 \u00a0UNIVERSAL SHIFT REGISTER
    \nMEMORIES (TTL)<\/strong>
    \n28 \u00a0\u00a0 \u00a0ORGANISATION OF RAM \/ IC 7489 – RAM
    \n29 \u00a0\u00a0 \u00a0ROM (READ ONLY MEMORY)
    \nEXPERIMENT OF CMOS DEVICES<\/strong>
    \n30 \u00a0\u00a0 \u00a0NAND CMOS
    \n31 \u00a0\u00a0 \u00a0NOR CMOS
    \n32 \u00a0\u00a0 \u00a0BOOLEAN ALGEBRA (CMOS)
    \n33\u00a0 \u00a0 \u00a0ASTABLE MULTIVIBRATOR & SCHMITT TRIGGER WITH ADJUSTABLE TRIGGERING (CMOS)
    \n34 \u00a0\u00a0 \u00a0MONOSTABLE MULTIVIBRATOR (CMOS)
    \n35 \u00a0\u00a0 \u00a0FLIP FLOPS (CMOS)
    \n36 \u00a0\u00a0 \u00a0HALF & FULL ADDER (CMOS)
    \n37 \u00a0\u00a0 \u00a0PRESETTABLE DEVIDE-BY-N COUNTER (CMOS)
    \n38 \u00a0\u00a0 \u00a0BINARY TO DECIMAL CONVERSION
    \n39 \u00a0\u00a0 \u00a03 DIGIT STROKE COUNTER USING IC 7490
    \n40 \u00a0\u00a0 \u00a0ACCURATE TIMER USING BEL CD 4045 & CD 4013
    \n41 \u00a0\u00a0 \u00a0MONOSTABLE OPERATION USING IC 555 TIMER
    \n42 \u00a0\u00a0 \u00a0ASTABLE OPERATION USING IC 555 TIMER
    \n43 \u00a0\u00a0 \u00a0FREQUENCY MODULATION USING IC 555 TIMER
    \n44 \u00a0\u00a0 \u00a0SQUARE WAVE GENERATOR USING IC 555 TIMER<\/p>\n","protected":false},"excerpt":{"rendered":"

    Computer Logic Training Board has been designed specifically for the study of Digital IC Circuits. Digital IC Trainer is a completely self contained, most versatile, sophisticated and economical.
    \nThe board is absolutely self contained and requires no other apparatus.
    \nPractical experience on this board carries great educative value for Science and Engineering Students.<\/p>\n